1. Field of the Invention
The present invention relates to a method for patterning a semiconductor component.
Although the present invention can be used in general terms for the patterning of a semiconductor component having first and second regions, the text which follows will describe the problems underlying the invention on the basis of the patterning of a memory cell of a DRAM memory.
2. Description of the Prior Art
In the text which follows, a generally known memory cell of a DRAM memory is described with reference to FIG. 3. The memory cell includes a storage capacitor 802 (capacitor), which is embedded in a semiconductor substrate 801, and a horizontal transistor.
The transistor has a channel region 860 in a horizontal surface of the semiconductor substrate 801. A node region 811 and a bit line region 812 are arranged opposite one another horizontally adjacent to the channel region 860. A gate stack 803 is provided vertically with respect to the channel region 860. When a suitable potential is applied to the gate stack 803, the bit line region 812 is conductively connected to the node region 811.
The capacitor 802 and the transistor are arranged in such a way that the capacitor is conductively connected to the node region 811. Therefore, when the transistor is switched to a conducting state, a current path results between the storage capacitor 802 and the bit line region 812. For the DRAM memory, the bit line region 812 is connected to a bit line. For operation of the DRAM memory, it is necessary for the bit line and therefore the current path to have a defined electrical resistance.
The production of the transistor and of the capacitor 802 is carried out in a plurality of production steps, using a plurality of photolithographic masks. Deviations in the positioning of the individual masks with respect to one another result in a variation in the distance between the capacitor 802 and the gate stack 803 of the transistor, i.e. the dimensions of the node region 811, resulting in an undesirable variation in the resistance of the above-described current path. Therefore, an additional doping 841, which compensates for the variation in the resistance, is introduced into the node region 811.
This additional doping should not affect the switching properties of the transistor. Therefore, this doping 841 is only implanted remote from the channel region 860, in a region of the node region 811 which adjoins the capacitor 841. This is achieved by implantation at an angle to the surface of the semiconductor substrate 801. In the bit line region 812, however, the doping 841 is implanted near to the channel region 860. On the other hand, different dopings have to be introduced into the bit line region 812, which need not be present in the first region 811. Consequently, generally known semiconductor production processes provide for the node region 811 first of all to be covered with a photolithographic mask and then for the doping in the bit line region 812 to be carried out. After the photo-lithographic mask has been removed, the node region 811 is covered with a second photolithographic mask, and then the bit line region 812 is doped.
For this purpose, the corresponding photolithographic masks have to be accurately patterned and positioned to within one third of the lateral feature size. For desired feature sizes of less than 50 nm, this requires accurate alignment to within 15 nm. Therefore, the corresponding photolithographic masks are also described as critical masks. This imposes very high demands on process steps and apparatuses used to apply the critical mask, involving inter alia the use of high-resolution primary masks, lithography in the ultraviolet spectral region, a correspondingly suitable photoresist, an accurate alignment of the primary mask and the semiconductor substrate 801 with respect to one another. A considerable depth of trenches between the gate stacks results in difficulties in the exposure of masks, on account of the limited focal depth of the pattern being exposed in the vertical direction.